CMP=0, LLWU=0, USBFS=0, UART3=0, CMT=0, IIC0=0, UART0=0, IIC1=0, UART1=0, EWM=0, VREF=0, UART2=0
System Clock Gating Control Register 4
| EWM | EWM clock gate control 0 (0): Clock is disabled. 1 (1): Clock is enabled. |
| CMT | CMT clock gate control 0 (0): Clock is disabled. 1 (1): Clock is enabled. |
| IIC0 | IIC0 clock gate control 0 (0): Clock is disabled. 1 (1): Clock is enabled. |
| IIC1 | IIC1 clock gate control 0 (0): Clock is disabled. 1 (1): Clock is enabled. |
| UART0 | UART0 clock gate control 0 (0): Clock is disabled. 1 (1): Clock is enabled. |
| UART1 | UART1 clock gate control 0 (0): Clock is disabled. 1 (1): Clock is enabled. |
| UART2 | UART2 clock gate control 0 (0): Clock is disabled. 1 (1): Clock is enabled. |
| UART3 | UART3 clock gate control 0 (0): Clock is disabled. 1 (1): Clock is enabled. |
| USBFS | USB FS clock gate control 0 (0): Clock is disabled. 1 (1): Clock is enabled. |
| CMP | Comparator clock gate control 0 (0): Clock is disabled. 1 (1): Clock is enabled. |
| VREF | VREF clock gate control 0 (0): Clock is disabled. 1 (1): Clock is enabled. |
| LLWU | LLWU Clock Gate Control 0 (0): Clock is disabled. 1 (1): Clock is enabled. |